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tb67s103aftg/fng 2014 - 01- 2 7 1 toshiba bicd integrated circuit silicon monolithic tb67s10 3 aftg, tb67s10 3 afng serial - in controlled bipolar stepping motor driver the tb67s103a is a two - phase bipolar stepping motor driver using a pwm chopper. the data bank setting function by serial c ontrol i/f is built in.fabricated with the bicd process, rating is 50 v/4.0 a . features ? bicd process integrated monolithic ic. ? capable of controlling 1 b ipolar stepping motor . ? pwm controlled constant - current drive . ? allows full, half , quarter , 1/8, 1/16, 1/32 step operation . ? id (2 bits) setup is possible. ? low on - resistance (high + low s ide=0.49 (typ)) mosfet output stage. ? high efficiency motor current control mechanism (advanced dynamic mixed decay) ? high voltage and current (for specification, please refer to absolute maximum ratings and operation ranges) ? error detection ( tsd/isd ) signal output function ? built- in error detection circuits (thermal shutdown (tsd) over - current shutdown (isd), and power - on reset (por)) ? built- in v cc regulator for internal circuit use. ? chopping frequency of a motor can be customized by external resist ance and condenser. ? multi packag e lineup tb67s10 3 aftg : p- wqfn48- 0707- 0.50- 003 tb67s10 3 afng: htssop48 -p- 300- 0.50 note) please be careful a bout thermal conditions during use . p - wqfn48 - 0707 - 0.50 - 003 htssop 48-p- 300- 0 .5 0 f t g weight 0.10g ( typ .) f n g w eight 0. 21 g ( typ .)
tb67s103aftg/fng 2014 - 01- 2 7 2 pin assignment (tb67s103a) please mount the four corner pins of the qfn package and the exposed pad to the gnd area of the pcb. please mount the exposed pad of the htssop package to the gnd area of the pcb. 1 2 3 4 5 6 7 15 16 17 18 19 20 28 29 30 31 32 33 34 42 43 44 45 46 47 48 21 oscm sclk so sdata sset nc nc nc outa+ outa+ nc nc gnd nc gnd nc nc nc outb+ outb+ nc nc vrefb id vrefa lo gnd nc fng (top view) 22 23 24 25 26 27 8 9 10 11 1 2 13 14 35 36 37 38 39 40 41 clk enable reset gnd nc rsa rsa outa - outa - gnd gnd outb - outb - nc rsb rsb vm nc vcc nc (top view) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 3 4 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 24 25 48 47 46 45 44 43 42 41 40 39 38 37 f t g nc clk enable reset gnd nc rsa rsa nc outa+ outa+ nc nc nc gnd outa - outa - gnd gnd outb - outb - gnd nc nc nc outb+ outb+ nc rsb rsb nc vm nc vcc nc nc nc lo id gnd vrefb vrefa oscm sclk so sdata sset nc
tb67s103aftg/fng 2014 - 01- 2 7 3 tb67s103 a block diagram functional blocks/circuits/constants in the block chart etc . may be omitted or simplified for explanatory purposes. sset sd ata sclk enable reset clk id vrefa vrefb motor oscillator oscm vcc regulator vcc tsd isd rsb motor control logic predriver rsa vm signal decode logic current refe rence setting current comp current comp predriver current level set power - on reset lo error output osc - clock converter system oscillator gnd id select serial b ank set + serial out so outa+ outa - outb+ outb -
tb67s103aftg/fng 2014 - 01- 2 7 4 application notes all the grounding wires of the tb6 7s103 a must run on the solder mask on the pcb and be externally terminated at only one point. also, a grounding method should be considered for efficient heat dissipation. careful attention should be paid to the layout of the output, vdd (vm ) and gnd traces, to avoid short circuits across output pins or to the power supply or ground. if such a short circuit occurs, the device may be permanently damaged. also, the utmost care should be taken for pattern designing and implementation of the device since it has power supply pins ( vm , rs , out, gnd) through which a particularly large current may run. if these pins are wired incorrectly, an operation e rror may occur or the device may be destroyed. the logic input pins must also be wired correctly. otherwise, the device may be damaged owing to a current running through the ic that is larger than the specified current.
tb67s103aftg/fng 2014 - 01- 2 7 5 pin explanations tb67s103 a ftg (qfn48) pin no.1 C 28 pin no. pin name function 1 nc non - connection pin 2 clk clk signal input pin 3 enable ach/bch o utput stage on/off control pin 4 reset electric angle reset pin 5 gnd ground pin 6 nc non - connection pin 7 rs a (*) motor ach current sense pin 8 rs a (*) motor ach current sense pin 9 nc non - connection pin 10 out a + (*) motor ach (+) output pin 11 out a + (*) motor ach (+) output pin 12 nc non - connection pin 13 nc non - connection pin 14 nc non - connection pin 15 gnd ground pin 16 out a- (*) motor ach ( - ) output pin 17 out a- (*) motor ach ( - ) output pin 18 gnd ground pin 19 gnd ground pin 20 out b- (*) motor bch ( - ) output pin 21 out b- (*) motor bch ( - ) output pin 22 gnd ground pin 23 nc non - connection pin 24 nc non - connection pin 25 nc non - connection pin 26 out b + (*) motor bch (+) output pin 27 out b + (*) motor bch (+) output pin 28 nc non - connection pin (*) note: please connect the pins with the same names, at the nearest point of the device. ? please do not run patterns under nc pins.
tb67s103aftg/fng 2014 - 01- 2 7 6 pin no.29 C 4 8 pin no. pin name function 29 rs b (*) motor bch current sense pin 30 rs b (*) motor bch current sense pin 31 nc non - connection pin 32 vm motor power supply pin 33 nc non - connec tion pin 34 vcc internal vcc regulator monitor pin 35 nc non - connection pin 36 nc non - connection pin 37 nc non - connection pin 38 lo error detect signal output pin 39 id id set pin 40 gnd ground pin 41 vref b motor bch output set pin 42 vref a motor ach output set pin 43 oscm oscillating circuit frequency for chopping set pin 44 sclk serial clock input pin 45 so serial data out put pin 46 sdata serial data in put pin 47 sset se t signal in put pin 48 nc non - connection pin (*) note: please connect the pins with the same names, at the nearest point of the device. ? please do not run patterns under nc pins.
tb67s103aftg/fng 2014 - 01- 2 7 7 pin explanations tb67s103 a fng (h ts sop 48) pin no.1 C 28 pi n no. pin name function 1 oscm oscillating circuit frequency for chopping set pin 2 nc non - connection pin 3 sclk serial clock input pin 4 so serial data out put pin 5 sdata serial data in put pin 6 nc non - connection pin 7 sset se t signal in put pin 8 clk clk signal input pin 9 enable ach/bch o utput stage on/off control pin 10 reset electric angle reset pin 11 gnd ground pin 12 nc non - connection pin 13 rs a (*) motor ach current sense pin 14 rs a (*) motor ach current sense pin 15 nc non - connec tion pin 16 out a + (*) motor ach (+) output pin 17 out a + (*) motor ach (+) output pin 18 nc non - connection pin 19 nc non - connection pin 20 gnd ground pin 21 nc non - connection pin 22 out a- (*) motor ach ( - ) output pin 23 out a- (*) motor ach ( - ) outpu t pin 24 gnd ground pin 25 gnd ground pin 26 out b- (*) motor bch ( - ) output pin 27 out b- (*) motor bch ( - ) output pin 28 nc non - connection pin (*) note: please connect the pins with the same names, at the nearest point of the device. ? please do not run patterns under nc pins.
tb67s103aftg/fng 2014 - 01- 2 7 8 pin no. 29 C 48 pin no. pin name function 29 gnd ground pin 30 nc non - connection pin 31 nc non - connection pin 32 out b + (*) motor bch (+) output pin 33 out b + (*) motor bch (+) output pin 34 nc non - connection pin 35 rs b (*) motor bch current sense pin 36 rs b (*) motor bch current sense pin 37 nc non - connection pin 38 nc non - connection pin 39 vm motor power supply pin 40 nc non - connection pin 41 vcc internal vcc regulator monitor pin 42 nc non - connection pin 43 nc non - connection pin 44 lo error detect signal output pin 45 id id set pin 46 gnd ground pin 47 vref b motor bch output set pin 48 vref a motor ach output set pin (*) note: please connect the pins with the same names, at the nearest point of the device. ? please do not run patterns under nc pins.
tb67s103aftg/fng 2014 - 01- 2 7 9 input/output equivalent circuit (tb67s103 a ) pin name in/out signal equivalent circuit sclk sdata sset clk enable reset digital input (vih/vil) vih: 2.0v(min)~5.5v(max) vil : 0v(min)~0.8v(max) so lo digital output (voh/vol) ( pullup resistance :10k 100k ) vcc vrefa vref b vcc voltage range 4.75v(min)~5.0v(typ)~5.25v(max) vref voltage range 0v~3.6v oscm oscm frequency setting range 0.64mhz(min)~1.12mhz(typ)~2.4mhz(max) out a+ outa - outb+ outb - rsa rsb vm power supply voltage range 10v(min)~47v(max) out pin voltage 10v(min)~47v(max) 100k 1 k gnd logic input pin logic o utput p in gnd 1k vcc gnd vref 500 1k oscm gnd gnd rs out+ out -
tb67s103aftg/fng 2014 - 01- 2 7 10 pin name in/out signal equivalent circuit id <1:1> r_id=open (5v set ) <1:0> r_id=100k (2.5v set ) <0:1> r_id=33k (1.25v set ) <0:0> r_id=gnd (0v set ) it is possible to change id setup of a device by attaching resistance (o r gnd short - circuit / open) to id terminal. when set up with id terminal and of a serial input are in agreement, the serial data inputted to the device are made to reflect. * the variation in resistance is 30%. the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 1 00k 1 k v cc id r_ id
tb67s103aftg/fng 2014 - 01- 2 7 11 function explanation (stepping motor) 1. clk function each up - edge of the clk signal will shift the motor s electrical angle per step. clk input function up- edge shifts t he electrical angle per step. down - edge (state of the electrical angle does not change.) 2. enable function the enable pin controls the on and off of the corresponding output stage. this pin serves to select if the motor is stopped in off (h igh impedance) mode or activated. p lease set the enable pin to l during vm power - on and power - off sequence. enable i nput function h output stage= on ( n ormal operation mode) l output stage= off) ( h igh impedance mode) 3. reset function reset input function h sets the electrical angle to the initial condition. l normal ope ration mode the current for each channel ( while reset is applied) is shown in the table below. mo will show l at this time. step resolution setting a ch current setting b ch current setting default electrical angle full step 100% 100% 45 half step (t ype (a)) 100% 100% 45 half step (type (b)) 71% 71% 45 quarter step 71% 71% 45 1/8 step 71% 71% 45 1/16 step 71% 71% 45 1/32 step 71% 71% 45
tb67s103aftg/fng 2014 - 01- 2 7 12 step resolution setting and initial angle [full step resolution] [half step resolution (type a)] mo output shown in the timing chart is when the mo pin is pulled up . timing charts may be simplified for explanatory purpose. h l h l +100% - 100% 0% +100% - 100% 0% mo iout(b) iout(a) clk cw ccw h l h l +100% - 100% 0% +100% - 100% 0% mo iout(b) iout(a) clk cw ccw
tb67s103aftg/fng 2014 - 01- 2 7 13 [half step resolution (type b)] [qua rter step resolution] timing charts may be simplified for explanatory purpose. h l h l +100% - 100% 0% +100% - 100% 0% mo iout(b) iout(a) clk +71% - 71% +71% - 71% +38% - 38% +38% - 38% cw ccw h l h l +100% - 100% 0% +100% - 100% 0% mo iout(b) iout(a) clk +71% - 71% +71% - 71% cw ccw
tb67s103aftg/fng 2014 - 01- 2 7 14 [1/8 step resolution] timing charts may be simplified for explanatory purpose. cw ccw h l h l mo clk +100% - 100% 0% iout(b) +100% - 100% 0% iout(a) +96% +83% +56% +38% +71% +20% +96% +83% +56% +38% +71% +20% - 96% - 83% - 56% - 38% - 71% - 20% - 96% - 83% - 56% - 38% - 71% - 20% - 98% +98% - 98% +98% mo
tb67s103aftg/fng 2014 - 01- 2 7 15 [1/1 6 step resolution] timing charts may be simplified for explanatory purpose. h l h l mo clk iout(b) +100% - 100% 0% iout(a) +96% +83% +56% +38% +71% +20% - 96% - 83% - 56% - 38% - 71% - 20% - 98% +98% - 100% 0% +96% +83% +56% +38% +71% +20% - 96% - 83% - 56% - 38% - 71% - 20% - 98% +98% +100% cw ccw mo
tb67s103aftg/fng 2014 - 01- 2 7 16 [1/32 step resolution] timing charts may be simplified for explanatory purpose. h l mo clk iout(b) +100% - 100% 0% iout(a) +100% - 100% 0% h l cw ccw m o
tb67s103aftg/fng 2014 - 01- 2 7 17 device distinction circuit ( id _select) id <0:0> <0:1> <1:0> <1:1> r_id=gnd - - - r_id=33k (1.25v set ) - - - r_id=100k (2.5v set ) - - - r_id=open - - - it is possible to change id setup of a device by attaching resistance (or gnd short - circuit / open) to id terminal. when set up with id terminal and of a serial input are in agreement, the serial data inputted to the device are made to reflect.
tb67s103aftg/fng 2014 - 01- 2 7 18 about serial input data ( tb67s103 a) a serial input is effective only when a sset pin is "h". a setup of operation is possible by 3 line serial input of "sc lk", "sdata", and "sset." specification of setup mode (timing chart) timing charts may be simplified for explanatory purpose. input data is 16 - bit composition (it decodes every 8 bits). please input serial data in order of the following. ( sset input is s witched to h from l ) ( initial setup input ) ( data setup input ) in order that tb67s103a may prevent the incorrect input of serial data, it is checked whether serial data have b een normally inputted in initial setup. (example) the case of ic of id setup ='00' data setup is received when initial setup='1011 0000' is inputted. data setup is not received when initial setup='1011 0 1 00' is inputted. data setup is not r eceived when in itial setup='1010 0 0 00' is inputted. please input 1011( s103 characteristic value ) into 4 bits of heads. in 1 to 4 bits= 1011 and 5 to 6 bits= id setup , serial data are received. 7 bits is an a/d setup. ( 0: address setup and 1: data setup) 8 bits is a w/r setup. (0: write mode and 1: read mode) in write mode, an address or data is set up by [data setup]. in read mode, it is possible to output the value (an address or data ) of a register from so pin . the input of serial data becomes effective only in sset=h. the serial data inputted between sset=l are not received. 1 0 1 1 id1 id0 a/d w/r d7 d6 d5 d4 d3 d2 d1 d0 sset s clk s data device distinction read/ writ e a ddress setting or d ata setting sset only the period of h has an effective serial input. initial setup data setup initial setup data setup a ddress/ d ata s erial - data inpu t distinction initial setup initial setup
tb67s103aftg/fng 2014 - 01- 2 7 19 about a serial input (initial setup data setup flow chart ) no serial input: effective/initial setup start chip select setup = 6 bits of input data heads? chip select check (6 bits of heads) 8bit s input no yes a/d bit=? a/d=0 a/d=1 address set data set w/r bit=? w/r=0 w/r=1 write mode read mode the end of initial setup a/d of initial setup? 8 - bit s address the address currently written in is outputted to so pin. a/d=1,w/r bit=0 8 - bit s data writing a/d=1,w/r bit=1 the data currently written in is outputted to so pin . a/d=0,w/r bit=0 a/d=0,w/r bit=1 sset=high yes serial input: don't receive. data setup: don't receive.
tb67s103aftg/fng 2014 - 01- 2 7 20 the change of a serial bank data bit function [a2] [a1] [a0] 0 0 0 i t is a serial - data input to bank0. 0 0 1 it is a serial - data input to bank 1 . 0 1 0 it is a serial - data input to bank 2 . 0 1 1 it is a serial - data input to bank 3 . 1 0 0 it is a serial - data input to bank 4 . 1 0 1 it is a serial - data input to bank 5 . 1 1 0 it is a serial - data input to bank 6 . 1 1 1 it is a serial - data input to bank 7 .
tb67s103aftg/fng 2014 - 01- 2 7 21 bank0 : motor drive: setup 1 (basic setup) data bit function [d7] [d6] 0 0 - dont care 0 1 - dont care 1 0 - do nt care 1 1 - dont care f oscm =1.6mhz(typ) motor drive torque setting data bit function [d5] [d4] 0 0 iout 40% ( *initial ) 0 1 iout 60% 1 0 iout 80% 1 1 iout 100% < d3> motor drive cw/ccw setting data bit function [d3] 0 ccw ( at the time of charge out + pin l, out - pin h) ( *initial ) 1 cw ( at the time of charge out + pin h, out - pin l) motor drive step resolution setting data bit function [d2] [d1] [d0] 0 0 0 standby mode ( power - saving mode ) (*initial) ( note ) 0 0 1 full step resolution 0 1 0 half step resolution(type (a)) 0 1 1 quarter step resolution 1 0 0 half step resolution(type (b)) 1 0 1 1/8 step resolution 1 1 0 1/16 step resolution 1 1 1 1/32 step resolution ( note ) standby mode : the oscm is disabled and the output stage is set to off status.
tb67s103aftg/fng 2014 - 01- 2 7 22 bank 1 : motor drive: setup 2 (basic setup) < d7:d6> motor drive decay mode setting data bit function [d7] [d6] 0 0 mixed decay mode ( *initial ) 0 1 slow decay only 1 0 fast decay only 1 1 auto decay mode * about a decay mode set ting please carry out change to auto decay mode ( =[1,1] ) after stopping a moto r. please carry out the change of =[0,0]/[0,1]/[1,0] ? [1,1] after stopping a motor. motor drive fchop setting data bit function [d5] [d4] 0 0 fchop=100khz ( *initial ) 0 1 fchop=50khz 1 0 fchop=66.6khz 1 1 t est mode (don t use) at the time of f oscm =1.6mhz(typ) set ting, fchop=100khz < d3:d2> motor drive mixed decay timing ( mdt ) setting data bit function [d3] [d2] 0 0 mdt=37.5% ( *initial ) 0 1 mdt=50% 1 0 mdt=25% 1 1 mdt=12.5% *about mdt setting only in mixed decay mode (=[0,0 ]) , this setup is effective. motor drive revolving speed setting data bit function [d1] [d0] 0 0 fclk 100% ( *initial ) 0 1 fclk 50% 1 0 fclk 25% 1 1 fclk 12.5% * when a setup of bank is changed during operation, it is reflected in the timin g of the next fchop start.
tb67s103aftg/fng 2014 - 01- 2 7 23 bank2 others: option setup (reference value) < d7:d6> error detection function isd mask ing time setting data bit function [d7] [d6] 0 0 8 1/foscs (1.25 s) ( *initial ) 0 1 4 1/foscs (0.625 s) 1 0 16 1/foscs (2 .5 s) 1 1 32 1/foscs (5.0 s) < d5:d4> error detection function tsd mask ing time setting data bit function [d5] [d4] 0 0 16 1/foscs (2.5 s) ( *initial ) 0 1 4 1/foscs (0.625 s) 1 0 8 1/foscs (1.25 s) 1 1 32 1/foscs (5.0 s) < d3:d2> error detection function vrs mask ing time setting data bit function [d3] [d2] 0 0 8 1/foscs (1.25 s) ( *initial ) 0 1 4 1/foscs (0.625 s) 1 0 16 1/foscs (2.5 s) 1 1 32 1/foscs (5.0 s) foscs=6.4mhz(typ) internal clock serial data: bank2 (isd mask ing time )/(vrs mask ing time ) in the case of 0,0 : about 1/foscs 7~8clk(1.09 s~1.25 s) in the case of 0,1 : about 1/foscs 3~4clk(0.47 s~0.63 s) in the case of 1 ,0 : about 1/(foscs/2) 7~8clk=1/foscs 14~16clk(2.5 s~2.8 s) in the case of 1,1 : about 1/(foscs/4) 7~8clk=1/foscs 32~36clk(5.0 s~5.6 s) foscs=6.4mhz(typ) internal clock serial data: bank2 (tsd mask ing time ) in the case of 0,0 : about 1/(foscs/2) 7~8clk=1/foscs 14~16clk(2.5 s~2.8 s) in the case of 0,1 : about 1/foscs 3~4clk(0.47 s~0.63 s) in the case of 1 ,0 : about 1/foscs 7~8clk(1.09 s~1.25 s) in the case of 1,1 : about 1/(foscs/4) 7~8clk=1/foscs 32~36clk(5.0 s~5.6 s) < d1:d0> motor drive digital tblank setting data bit function [d1 ] [d 0 ] 0 0 2 1/foscm ( *initial ) 0 1 3 1/foscm 1 0 4 1/foscm 1 1 6 1/foscm f oscm =1.6mhz(typ) * when a setup of bank is changed during operation, it is reflected in the timing of the next fchop start.
tb67s103aftg/fng 2014 - 01- 2 7 24 lo(error detect signal) output function when thermal shutdown(tsd) or over - current shutdown(isd ) is applied, the lo voltage will be switched to lo w(gnd) level. the lo is an open - drain output pin. lo pin needs to be pulled up to 3.3v/5.0v level for proper function . during regular operation, the lo pin level will stay high(vcc leve l). when error detection (tsd, isd) is applied, the lo pin will show low (gnd) level. 3.3v 10k
tb67s103aftg/fng 2014 - 01- 2 7 25 decay function admd( advanced dynamic mixed decay ) c onstant current control the advanced dynamic mixed decay threshold, which deter mines the current ripple level during current feedback control, is a unique value. auto decay mode current waveform timing charts may be simplified for explanatory purpose. nf detect fchop internal osc adm dth ( advanced dynamic mixed decay threshold ) fchop 1 cycle 16clk c harge m ode nf detect fast decay admdth detect slow decay fchop 1 cycle charge mode iout s etting current value detect nf detect nf detect s etting current value internal osc iout fchop fchop advanced dynamic mixed decay threshold admdth fast decay slow decay
tb67s103aftg/fng 2014 - 01- 2 7 26 admd current waveform ? when the next current step is higher : ? when charge period is more than 1 fchop c ycle : when the charge period is longer than fchop cycle, the charge period will be extended until the motor current reaches the nf threshold. once the current reaches the next current step, then the sequence will go on to decay mode. s etting current value slow slow slow slow f ast f ast charge charge f ast charge fast charge s etting current value nf nf nf nf internal osc fchop fchop fchop fchop s etting current value slow slow slow f ast f ast charge charge fast charge s etting current value nf nf nf internal osc fchop fchop fcho p fchop
tb67s103aftg/fng 2014 - 01- 2 7 27 ? when the next current step is low er : ? when the fast continues past 1 fchop cycle (the motor current not reaching the admd threshold during 1 fchop cycle) s etting current value f ast nf nf nf the operation mode will be switched to charge to monitor the motor current with the rs comparator; then will be switched to fast because the motor current is above the threshold. f chop f chop f chop f chop s etting current value internal osc slow f ast charge slow f ast charge f ast slow slow charge c harge s etting current value f ast nf nf the operation mode will be switched to charge to monitor the motor current with the rs comparator; then will be switched to fast because the motor current is above the threshold. f chop f chop f chop f chop s etting current value internal osc slow f ast charge f ast charge slow slow charge if the motor current is still above the admd threshold after reaching 1 fchop cycle, the output stage function will stay fast until the current reaches the admdth.
tb67s103aftg/fng 2014 - 01- 2 7 28 mixed decay mode current waveform fast decay (only) mode current waveform slow decay (only) mode current waveform timing charts may be simplified for explanatory purpose. nf 37.5 % m dt d ecay m ode 1 f chop internal osc c harge m ode nf detect s low m ode m ixed d ecay t iming (mdt) f ast m ode c harge mode 12 .5% m dt 25.0 % m dt 50.0 % m dt mdt nf d ecay m ode 1 f chop internal osc c harge m ode nf detect f ast m ode c harge mode nf d ecay m o de 1 f chop internal osc c harge m ode nf detect s low m ode c harge mode mdt does not occur. s etting current value s etting current value s etting current value mdt does not occur.
tb67s103aftg/fng 2014 - 01- 2 7 29 output transistor function mode output transistor function mode u1 u2 l1 l2 charge on off off on slow off off on on fast off on on o ff note: this table shows an example of when the current flows as indicated by the arrows in the figures shown above. if the current flows in the opposite direction, refer to the following table. mode u1 u2 l1 l2 charge off on on off slow off off on on fast on off off on this ic controls the motor current to be constant by 3 modes listed above. the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. u1 l1 u2 l2 pgnd off off u1 l1 u2 l2 off on on load pgnd u1 l1 u2 l2 load pgnd rspin rrs vm on on load charge mode a current flows into th e motor coil. slow mode a current circulates around the motor coil and this device. fast mode the energy of the motor coil is fed back to the power on rs pin rrs vm rs pin rrs vm off off on off
tb67s103aftg/fng 2014 - 01- 2 7 30 calculation of the predefined output current for pw m constant - current control, this ic uses a clock generated by the oscm oscillator. the peak output current (s etting current value ) can be set via the current - sensing resistor (r s) and the reference voltage (vref), as follows: io ut(max) = vref(gain) vref(gain) : the vref decay rate is 1/ 5.0 (typ.) for example : in the case of a 100% setup when vref = 3 .0 v, torque=100%,rs=0.51 , the motor constant current ( s etting current value ) will be calculated as: i out = 3.0 v / 5 .0 / 0.51 = 1.18 a calculation of the oscm oscillation frequency (chopper reference frequency) an approximation of the oscm oscillation frequency (foscm) and chopper frequency (fchop) can be calculated by the following expressions. foscm=1/[0. 56 x{cx(r1 +500)}] c,r1: external co mponents for oscm (c=270pf , r 1 = 5.1 k? => about foscm= 1.12mhz(typ.) ) fchop = foscm / 16 foscm= 1.12mhz => fchop = about 70khz if chopping frequency is raised, rippl of current will become small and wave - like rep roducibility will improve. however, the gate loss inside ic goes up and generation of heat becomes large. by lowering chopping frequency, reduction in generation of heat is expectable. however, rippl of current may become large. it is a standard about ab out 70 khz. a setup in the range of 50 to 100 khz is recommended. vref(v) r rs ()
tb67s103aftg/fng 2014 - 01- 2 7 31 absolute maximum ratings (ta = 25 c ) note 1: usually, the maximum current value at the ti me should use 70% (i out Q2. 8 a) or less of the a bsolute m aximum r atings for a standard on thermal rating. the maximum output current may be further limited in view of thermal considerations, depending on ambient temperature and board conditions. note 2: dev ice alone (ta =25c) when ta exceeds 25 o c, it is necessary to do the derating with 10.4 mw/ o c. ta: ambient temperature topr : ambient temperature while the ic is active tj: junction temperature while the ic is active. the maximum junction temperature is li mited by the thermal shutdown (tsd) circuitry. it is advisable to keep the maximum current below a certain level so that the maximum junction temperature, tj (max), will not exceed 120c. caution absolute maximum ratings the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating (s) may cause device breakdown, damage or de terioration, and may result in injury by explosion or combustion. the value of even one parameter of the absolute maximum ratings should not be exceeded under any circumstances. this product does not have overvoltage detection circuit . th erefore, the device is damaged if a voltage exceeding its rated maximum is applied. all voltage ratings, including supply voltages, must always be followed. the other notes and considerations described later should also be referred to. operation ranges (t a= - 20 to 85 c ) characteristics symbol min typ. max unit remarks motor power supply vm 10 24 47 v - motor output current iout - 1.5 3.0 a (note 1) logic input voltage vin(h) 2.0 - 5.5 v logic input high level vin(l) 0 - 0.8 v logic input low level s o output pin voltage v s o - 3.3 5.0 v - lo output pin voltage vlo - 3.3 5.0 v - clock input frequency fclk - - 1 00 khz - chopper frequency fchop(range) 40 70 150 khz - vref input voltage vref gnd 2.0 3.6 v - note 1: maximum current for actual usage may be limited by the operating circu mstances such as operating conditions (exciting mode, operating time, and so on), ambient temperature, and heat conditions (board condition and so on). characteristics symbol rating unit remarks motor power supply vm 50 v - motor output voltage vout 50 v - motor output current io ut 4.0 a (note 1) internal logic power supply vcc 6 .0 v when externally applied. logic input voltage vin(h) 6 .0 v - vin(l) - 0.4 v - s o output voltage v s o 6 .0 v - lo output voltage vlo 6 .0 v - s o inflow current i s o 30 ma - lo inflow current ilo 30 ma - power dissipation w qfn48 pd 1.3 w (note 2) htssop48 pd 1.3 w (note 2) operating temperature topr - 20 to 85 c - storage temperature tstr - 55 to 150 c - junction temperature tj(max) 150 c -
tb67s103aftg/fng 2014 - 01- 2 7 32 electrical specifications 1 (ta = 25 c, vm = 24 v, unless specified otherwise) characteristics symbol test condition min typ. max unit logic input voltage high vin(h) logic input (note) 2 .0 - 5. 5 v low v in(l) logic input (note) 0 - 0.8 v logic input hysteresis voltage v in(hys) logic input (note) 100 - 300 mv logic input current high iin(h) logic input of m easurement =3.3 v - 33 - a low iin(l) logic input of m easurement =0v - - 1 a so output pin voltage low vol( so) iol=24ma output=low - 0.2 0.5 v lo output pin voltage low vol(lo) iol=24ma output=low - 0.2 0.5 v power consumption im1 o utput pins=open standby mode - 2 3 .5 ma im2 output pins=open standby release enable=low - 3.5 5.5 ma im3 output pins=open full step resolution - 5 .5 7 ma output leakage current high - side ioh vrs=vm=5 0v, vout =0v - - 1 a low - side iol vrs=vm=vout = 5 0v 1 - - a motor current channel differential iout1 current differential between ch - 5 0 5 % motor current setting accuracy iout2 iout =1 .5 a - 5 0 5 % rs pin current irs vrs = vm =24v 0 - 10 a motor output on - resistance (high - side+low - side) ron(h+l) tj=25 c , forward direction (high - side+low - side) h 0.49 0.6 note: vin (h) is defined as the vin voltage that causes the outputs (outa +/ -, outb +/ - ) to change when a pin under test is gradually raised from 0 v. v in (l) is defined as the v in voltage that causes the outputs (outa +/ - , outb +/ -) to change when the pin is then gradually lowered. the difference between v in (h) and v in (l) is defined as th e v in (hys). note: when the logic signal is applied to the device whilst the vm power supply is not asserted; th e device is designed not to function , but for safe usage, please apply the logic signal after the vm power supply is asserted and the vm voltage reaches the proper operating range.
tb67s103aftg/fng 2014 - 01- 2 7 33 electrical specifications 2 (ta = 25c, v m = 24 v , unless specified otherwise ) characteristics symbol test condition min typ. max unit vref input current i ref v ref = 2 .0v - 0 1 a vcc voltage vcc icc=5.0ma 4.75 5.0 5.25 v vcc current icc vcc=5.0v - 2.5 5 ma vref gain rate v ref (gain) v ref =2.0v 1/ 5. 2 1/5.0 1/ 4.8 thermal shutdown(tsd) threshold (note1) t j tsd 145 1 60 175 qc vm recovery voltage vmr 7.0 8.0 9.0 v over - current detection (isd) threshold ( note 2) isd 4.1 4.9 5.7 a note1: about tsd when the junction temperature of the device rea ched the tsd threshold, the tsd circuit is triggered; the internal reset circuit then turns off the output transistors. noise rejection blanking time is built - in to avoid misdetection. once the tsd circuit is triggered, the device will be set to standby mo de, and can be cleared by reasserting the vm power source, or reinput of serial data after a standby (bank0 = [0, 0, 0]) setup. the tsd circuit is a backup function to detect a thermal error, therefore is not recommended to be used aggressively. no te2: about isd when the output current reaches the threshold, the isd circuit is triggered; the internal reset circuit then turns off the ou tput transistors. once the isd circuit is triggered, the device keeps the output off until power - on reset (por), is reasserted or reinput of serial data after a standby (bank0 = [0, 0, 0]) setup. for fail - safe, please insert a fuse to avoid secondary trouble. back - emf while a motor is rotating, there is a timing at which power is fed back to the power supply. a t that timing, the motor current recirculates back to the power supply due to the effect of the motor back - emf. if the power supply does not have enough sink capability, the power supply and output pins of the device might rise above the rated voltages. th e magnitude of the motor back - emf varies with usage conditions and motor characteristics. it must be fully verified that there is no risk that the ic or other components will be damaged or fail due to the motor back - emf. cautions on overcur rent shutdown (isd) and thermal shutdown (tsd) the isd and tsd circuits are only intended to provide temporary protection against irregular conditions such as an output short - circuit; they do not necessarily guarantee the complete ic safety. if the device is used beyond the specified operating ranges, these circuits may not operate properly: then the device may be damaged due to an output short - circuit. the isd circuit is only intended to provide a temporary protection against an output short - circuit. if su ch a condition persists for a long time, the device may be damaged due to overstress. overcurrent conditions must be removed immediately by external hardware. ic mounting do not insert devices incorrectly or in the wrong orientation. otherwise, it may cau se breakdown, damage and/or deterioration of the device.
tb67s103aftg/fng 2014 - 01- 2 7 34 ac electrical specification (ta = 25 c, vm = 24 v, 6.8 mh/5.7 ? ) characteristics symbol test condition min typ. max unit inside filter of clk input minimum high width tclk(h) the clk(h ) minimum pulse width 300 - - ns inside filter of clk input minimum low width tclk(l) the clk( l ) minimum pulse width 250 - - ns output transistor switching specific tr - 30 80 130 ns tf - 40 90 140 ns tplh (clk) clk - output - 1000 - ns tphl (clk) clk - output - 1500 - ns analog noise blanking time atblk vm=24v,i out =1.5 a analog t blank 250 4 00 550 ns oscillator frequency accuracy ? foscm cosc=270pf, rosc=5.1 k -15 - +15 % oscillator reference frequency fosc m cosc = 270 pf, rosc = 5.1 k? 952 1120 1288 khz chopping frequency fchop output:active (i out = 1. 5 a), fosc = 1 12 0 khz - 7 0 - khz ac electrical specification timing chart timing charts may be simplified for explanatory purpose. tclk(h) t clk(l) tplh(clk) tphl(clk) 10% 90% tr 90% 10% tf clk out 50% 50% 50% 50% 50% 1/fclk
tb67s103aftg/fng 2014 - 01- 2 7 35 package dimensions (unit :mm) p - wqfn48 - 0707- 0.50 - 003
tb67s103aftg/fng 2014 - 01- 2 7 36 package dimensions (unit :mm) htssop48 - p - 300- 0.50
tb67s103aftg/fng 2014 - 01- 2 7 37 notes on contents block diagrams some of the functional blocks, circuits, or constants in the blo ck diagram may be omitted or simplified for explanatory purposes. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. timing charts timing charts may be simplified for explan atory purposes. application circuits the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required, especially at the mass - production design stage . toshiba does not grant any license to any indus trial property rights by providing these examples of application circuits. test circuits components in the test circuits are used only to obtain and confirm the device characteristics. these components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. ic usage considerations notes on handling of ics (1) the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings.exceeding the rating(s) may cause device breakdown, damage or deterioration, and may result in injury by explosion or combustion. (2) do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative te rminals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause device breakdown, damage or deterioration, and may result in injury by explosion or combustion. in addition, do not use any device inserted in the wrong orientation or incorrectly to which current is applied even just once . (3 ) use an appropriate power supply fuse to ensure that a large current does not continuously flow in the case o f overcurrent and/or ic failure. the ic will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead to smoke or ignition. to minimize the effects of the flow of a large current in the case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (4 ) if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunc tion or breakdown caused by the current resulting from the inrush current at power on or the negative current resulting from the back electromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics wit h built - in protection functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. (5) carefully select external components (such as inputs and negative feedbac k capacitors) and load components (such as speakers), for example, power amp and regulator. if there is a large amount of leakage current such as from input or negative feedback condenser , the ic output dc voltage will increase. if this output voltage is connected to a speaker with low input withstand voltage, overcurrent or ic failure may cause smoke or ignition. (the overcurrent may cause smoke or ignition from the ic itself.) in particular, please pay attention when using a bridge tied load (btl) connec tion - type ic that inputs output dc voltage to a speaker directly.
tb67s103aftg/fng 2014 - 01- 2 7 38 points to remember on handling of ic s overcurrent detection circuit overcurrent detection circuits (referred to as current limiter circuits) do not necessarily protect ics under all circum stances. if the overcurrent detection circuits operate against the overcurrent, clear the overcurrent status immediately . depending on the method of use and usage conditions, exceeding absolute maximum ratings may cause the overcurrent detection circuit t o operate improperly or ic breakdown may occur before operation. in addition, depending on the method of use and usage conditions, if overcurrent continues to flow for a long time after operation, the ic may generate heat resulting in breakdown. thermal s hutdown circuit thermal shutdown circuits do not necessarily protect ics under all circumstances. if the thermal shutdown circuits operate against the over - temperature, clear the heat generation status immediately . depending on the method of use and usage conditions, exceeding absolute maximum ratings may cause the thermal shutdown circuit to operate improperly or ic breakdown to occur before operation. heat radiation design when using an ic with large current flow such as power amp, regulator or driver, design the device so that heat is appropriately radiated, in order not to exceed the specified junction temperature (tj) at any time or under any condition. these ics generate heat even during normal use. an inadequate ic heat radiation design can lead to decrease in ic life, deterioration of ic characteristics or ic breakdown. in addition, when designing the device, take into consideration the effect of ic heat radiation with peripheral components. back - emf when a motor rotates in the reverse direction, s tops or slows abruptly, current flows back to the motors power supply owing to the effect of back - emf. if the current sink capability of the power supply is small, the devices motor power supply and output pins might be exposed to conditions beyond the a bsolute maximum ratings. to avoid this problem, take the effect of back - emf into consideration in system design.
tb67s103aftg/fng 2014 - 01- 2 7 39 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to mak e changes to the information in this document, and related hardware, software and systems (collectively "product") without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with tos hiba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for comp lying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or da mage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes f or product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the i nstructions for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own pr oduct design or applications, including but not limited to (a) determining the appropriateness of the use of th is product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? 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